Modern computer systems typically include a processor and various other components that are coupled together. In addition, many systems include one or more peripheral or input/output (IO) devices.
To enable communications between software that executes on the processor and operations that may be performed by the other devices, different mechanisms can be used. Common mechanisms include a polling method and an interrupt method. However, neither of these methods is optimal. Using a polling technique, software either continuously polls status registers on the IO device if the IO device's task is fine-grained, or relies on an asynchronous interrupt through the operating system (OS) if the IO device's task is coarse-grained. While a polling method may ensure good performance, it suffers from drawbacks. First, the core/thread that needs to know the completion status has to continuously check (e.g., via a busy spin operation) on a memory mapped input/output (MMIO) status register, preventing itself from entering a low power state. Second, repetitive polling on an uncacheable MMIO address results in a large amount of traffic on a system interconnect. In a word, the fast response time comes at a cost of power consumption (a major issue especially for ultra-low power environments) and waste of system resources.
An interrupt method avoids busy spinning of a processor on the status register. While waiting, the core/thread can either context switch to execute another process or enter a lower power state. Completion of the task on the IO device triggers an interrupt into the OS. However, in a typical system, several hundred cache misses and tens of thousand clock cycles are induced by a kernel interrupt handler. This performance overhead of interrupt handling is not acceptable for many fine-grained logic blocks.
Thus both polling and interrupt techniques are not satisfactory for a low power application, as polling negates a large portion of any power benefits from using an IO device, while interrupts introduce a large performance penalty.